Double polysilicon technology, as described for example in U.S. Pat. No. 3,984,822, is particularly suitable for high density random access memory (RAM) and charge controlled devices (CCD). These devices are the major elements in memories for data processing systems. Increased device densities can be obtained in RAMs and CCDs by placing a contact to the second polysilicon conductor directly over the first polysilicon conductor. Such a contact placement, however, may be impacted by a "polysilicon void phenomenon". Laboratory experience indicates that polysilicon layers become porous due to grain growth and restructuring occurs during subsequent high temperature processes. Voids occur in the polycrystalline structure during the restructuring and may impact a contact structure, as will now be described.
When a protective insulating layer on overlying polysilicon conductors is etched to form contact openings, the etchant, typically hydrofluoric acid, in many instances, passes through a void in the restructured polycrystalline conductor to reach and etch through the insulating layer, typically silicon dioxide, separating the first polysilicon layer (poly 1) from the second polysilicon layer (poly 2). A direct short is formed between the first and second polysilicon layers when the contact opening is filled with a metal material. These poly 1 to poly 2 shorts lower the yields in RAMs and CCDs which increases device costs. Also, the poly 1 to poly 2 shorts require the circuit layout to be altered to lessen the shorts. These revised layouts require increased chip area to permit contacts to be formed in the poly 2 layer which are not directly over the poly 1 layer.
In the prior art, a similar phenomenon is described in U.S. Pat. No. 3,844,831 issued Oct. 29, 1974 and assigned to the present assignee. U.S. Pat. No. 3,844,831 describes a "tunneling phenomenon" in a multilevel metallurgy system for semiconductor devices. The "tunneling phenomenon" arises due to a misalignment between a contact opening or via and the metal levels to be connected together. When misalignment occurs, which frequently happens, the etchant tunnels through the exposed area including the common dielectric between the metallurgies as well as the dielectric separating the lower metallurgy from the semiconductor substrate. When the misaligned contact opening is filled with metal, a direct short is made to the semiconductor substrate by both metal layers. U.S. Pat. No. 3,844,831 solves the problem by forming a different dielectric between the lower level metallurgy and the substrate than the dielectric between the upper and lower metal levels. Essentially, the different dielectric is an etch stop to the etchant forming the contact opening to permit the joining together of the upper and lower metal levels but not the substrate with the metal levels. The problem of polysilicon void "phenomenon" is not addressed in U.S. Pat. No. 3,844,831 because the conductors are metal and not polysilicon. Further, the contact opening problem in double polysilicon exists whether or not misalignment occurs because the "polysilicon void phenomenon" exists in the polysilicon conductors and not in the insulating layers.